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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS21962-S PS21962-S
TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE
PS21962-S
INTEGRATED POWER FUNCTIONS
600V/5A low-loss 5th generation IGBT inverter bridge for three phase DC-to-AC power conversion. Open emitter type.
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
* * * * For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply). Input interface : 3V, 5V line (High Active).
APPLICATION AC100V~200V inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
38 0.5 20x1.778 (=35.56 ) 35 0.3 A 0.5 1 B 3.5 1.5 0.05
Dimensions in mm
TERMINAL CODE 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. (VNC) VUFB VVFB VWFB UP VP WP VP1 VNC* UN VN WN VN1 FO CIN VNC* VNO NW NV NU W V U P NC
17
(1)
14.4 0.5
0.4
(3.5)
0.28 1.778 0.2
33.7 0.5
Code
18 0.28 2.54 0.2
Lot No.
18.9 0.5 14.4 0.5
2-
R1
.6
QR
Type name
12
29.2 0.5
24 0.5
0.8 HEAT SINK SIDE
25
0.6 4-C1.2
0.4
3.08 14x2.54 (=35.56) 0.5 0.5 0.5
(0.678) 0.5 (0.678)
(3.3)
9.5 0.5
5.5 0.5
(1.2)
HEAT SINK SIDE
(1.2) DETAIL A DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open.
(0~5)
1.5m
in
Jun. 2005
MITSUBISHI SEMICONDUCTOR
PS21962-S
TRANSFER-MOLD TYPE INSULATED TYPE
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCC VCC(surge) VCES IC ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-NU, NV, NW Applied between P-NU, NV, NW TC = 25C TC = 25C, less than 1ms TC = 25C, per 1 chip (Note 1) Ratings 450 500 600 5 10 21.3 -20~+125 Unit V V V A A W C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ TC 100C). However, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ TC 100C).
CONTROL (PROTECTION) PART
Symbol VD VDB VIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VNC, VN1-VNC Applied between VUFB-U, VVFB-V, VWFB-W Applied between UP, VP, WP, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings 20 20 -0.5~VD+0.5 -0.5~VD+0.5 1 -0.5~VD+0.5 Unit V V V V mA V
TOTAL SYSTEM
Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature TC Tstg Storage temperature Viso Isolation voltage Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125C, non-repetitive, less than 2s (Note 2) 60Hz, Sinusoidal, 1 minute, All connected pins to heat-sink plate Ratings 400 -20~+100 -40~+125 1500 Unit V C C Vrms
Note 2: TC measurement point
Control terminals
DIP-IPM
11.6mm
3mm
IGBT chip position FWD chip position Power terminals
TC point Heat sink side
Jun. 2005
MITSUBISHI SEMICONDUCTOR
PS21962-S
TRANSFER-MOLD TYPE INSULATED TYPE
THERMAL RESISTANCE
Symbol Rth(j-c)Q Rth(j-c)F Parameter Junction to case thermal resistance (Note 3) Condition Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Min. -- -- Limits Typ. -- -- Max. 4.7 5.4 Unit C/W C/W
Note 3 : Grease with good thermal conductivity should be applied evenly with about +100m~+200m on the contacting surface of DIP-IPM and heat-sink. The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3C/W when the grease thickness is 20m and the thermal conductivity is 1.0W/m*k.
ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWD forward voltage Condition VD = VDB = 15V IC = 5A, Tj = 25C VIN = 5V IC = 5A, Tj = 125C Tj = 25C, -IC = 5A, VIN = 0V VCC = 300V, VD = VDB = 15V IC = 5A, Tj = 125C, VIN = 0 5V Inductive load (upper-lower arm) Tj = 25C Tj = 125C Min. -- -- -- 0.50 -- -- -- -- -- -- Limits Typ. 1.70 1.80 1.70 1.00 0.30 0.30 1.40 0.50 -- -- Max. 2.20 2.30 2.20 1.60 -- 0.50 2.00 0.80 1 10 Unit V V s s s s s mA
Switching times
Collector-emitter cut-off current
VCE = VCES
CONTROL (PROTECTION) PART
Symbol Parameter Condition Total of VP1-VNC, VN1-VNC VD = VDB = 15V VIN = 5V VUFB-U, VVFB-V, VWFB-W Total of VP1-VNC, VN1-VNC VD = VDB = 15V VIN = 0V VUFB-U, VVFB-V, VWFB-W VSC = 0V, FO terminal pull-up to 5V by 10k VSC = 1V, IFO = 1mA Tj = 25C, VD = 15V (Note 4) VIN = 5V Trip level Reset level Tj 125C Trip level Reset level (Note 5) Min. -- -- -- -- 4.9 -- 0.43 0.70 10.0 10.5 10.3 10.8 20 -- 0.8 0.35 Limits Typ. -- -- -- -- -- -- 0.48 1.00 -- -- -- -- -- 2.1 1.3 0.65 Max. 2.80 0.55 2.80 0.55 -- 0.95 0.53 1.50 12.0 12.5 12.5 13.0 -- 2.6 -- -- Unit
ID
Circuit current
mA
VFOH VFOL VSC(ref) IIN UVDBt UVDBr UVDt UVDr tFO Vth(on) Vth(off) Vth(hys)
Fault output voltage Short circuit trip level Input current Control supply under-voltage protection Fault output pulse width ON threshold voltage OFF threshold voltage ON/OFF threshold hysteresis voltage
Applied between UP, VP, WP, UN, VN, WN-VNC
V V V mA V V V V s V V V
Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating. 5 : Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure.
Jun. 2005
MITSUBISHI SEMICONDUCTOR
PS21962-S
TRANSFER-MOLD TYPE INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter Mounting torque Condition Mounting screw : M3 Recommended : 0.69 N*m (Note 6) (Note 7) Min. 0.59 -- -50 Limits Typ. -- 10 -- Max. 0.78 -- 100 Unit N*m g m
Weight Heat-sink flatness Note 6 : Plain washers (ISO 7089~7094) are recommended.
Note 7: Flatness measurement position
Measurement position
+-
4.6mm
DIP-IPM
Heat sink side
- +
Heat sink side
RECOMMENDED OPERATION CONDITIONS
Symbol VCC VD VDB VD, VDB tdead IO Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time Allowable r.m.s. current Condition Applied between P-NU, NV, NW Applied between VP1-VNC, VN1-VNC Applied between VUFB-U, VVFB-V, VWFB-W For each input signal, TC 100C VCC = 300V, VD = VDB = 15V, fPWM = 5kHz P.F = 0.8, sinusoidal output, (Note 8) fPWM = 15kHz Tj 125C, TC 100C Recommended value Min. Typ. Max. 0 13.5 13.0 -1 1.5 -- -- 300 15.0 15.0 -- -- -- -- -- -- -- 400 16.5 18.5 1 -- 2.5 Arms 1.5 -- -- 5.0 s V Unit V V V V/s s
0.5 PWIN(on) Allowable minimum input 0.5 PWIN(off) pulse width (Note 9) VNC variation -5.0 VNC Between VNC-NU, NV, NW (including surge) Note 8 : The allowable r.m.s. current value depends on the actual application conditions. 9 : IPM might not make response if the input signal pulse width is less than the recommended minimum value.
Jun. 2005
MITSUBISHI SEMICONDUCTOR
PS21962-S
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 2 THE DIP-IPM INTERNAL CIRCUIT
VUFB
HVIC IGBT1 Di1
DIP-IPM
P
VUB
VP1 UP VNC
VCC
UP
COM
UOUT
VUS
U
VVFB VP
VVB VP
IGBT2
VOUT VVS
Di2
V
VWFB WP
VWB WP
IGBT3
WOUT VWS
Di3
W IGBT4 Di4
LVIC
UOUT
VN1
VCC
NU IGBT5
VOUT
Di5
UN VN WN
Fo
UN VN WN Fo WOUT CIN VNO
NV IGBT6 Di6
NW
VNC
GND
VNO
CIN
Jun. 2005
MITSUBISHI SEMICONDUCTOR
PS21962-S
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 3 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current. a2. Short circuit detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO output (tFO(min) = 20s). a6. Input "L" : IGBT OFF. a7. Input "H" : IGBT ON. a8. IGBT OFF in spite of input "H".
Lower-arms control input Protection circuit state SET
a6 a7
RESET
Internal IGBT gate a2 a1 Output current Ic Sense voltage of the shunt resistor SC
a3
a4 a8 SC reference voltage
CR circuit time constant DELAY Error output Fo a5
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT OFF in spite of control input condition. b5. FO output (tFO 20s and FO output continuously during UV period). b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDr
RESET
SET
RESET b6
Control supply voltage VD
b1
UVDt
b3 b4
b2 Output current Ic
b7
Error output Fo
b5
Jun. 2005
MITSUBISHI SEMICONDUCTOR
PS21962-S
TRANSFER-MOLD TYPE INSULATED TYPE
[C] Under-Voltage Protection (Upper-arm, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UVDBt). c4. IGBT OFF in spite of control input signal level, but there is no FO signal output. c5. Under voltage reset (UVDBr). c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDBr Control supply voltage VDB
RESET
SET
RESET
c1
UVDBt
c5 c3 c4 c6
c2 Output current Ic High-level (no fault output) Error output Fo
Fig. 4 RECOMMENDED MCU I/O INTERFACE CIRCUIT
5V line
10k
DIP-IPM
UP,VP,WP,UN,VN,WN
MCU
Fo VNC(Logic)
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the wiring impedance of the printed circuit board. The DIP-IPM input section integrates a 3.3k (min) pull-down resistor. Therefore, when using an external filtering resistor, pay attention to the turn-on threshold voltage.
3.3k
Fig. 5 WIRING CONNECTION OF SHUNT RESISTOR
Wiring inductance should be less than 10nH.
DIP-IPM
Equivalent to the inductance of a copper pattern with length=17mm, width=3mm, and thickness=100m Shunt resistor
VNC VNO
NU NV NW
Please make the GND wiring connection of shunt resistor to the VNO, VNC terminal as close as possible.
Jun. 2005
MITSUBISHI SEMICONDUCTOR
PS21962-S
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 6 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2F R-category ceramic capacitor for noise filtering
C2 C1
C2 C1 C2 C1
Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
VUFB HVIC VP1
C3 VCC UP VUB UOUT VUS
VVFB
VWFB
DIP-IPM
P
UP
U
VVB
VP
VP
VOUT VVS
V
M
VWB
WP VNC
CONTROLLER
WP COM
WOUT VWS
W
LVIC
UOUT
VN1
5V line C3
VCC
NU
VOUT
UN VN WN Fo
UN VN WN WOUT Fo CIN VNO
NV
NW C
VNC
GND VNO
Too long wiring here might cause short-circuit.
CIN
15V line
Long GND wiring here might generate noise to input and cause IGBT malfunction.
If this wiring is too long, the SC level fluctuation might be large and cause SC malfunction.
A + Vref + Vref OR Logic + Vref Comparator B R1 C4 B R1 C4 B R1 C4 N1
Shunt resistors
External protection circuit
Note 1 2 3 4 5 6 7 8 9 10 11 12 13
: To prevent malfunction, the wiring of each input should be as short as possible (2~3cm). : By virtue of integrating HVIC inside, direct coupling to MCU without opto-coupler or transformer isolation is possible. : FO output is open drain type. It should be pulled up to a 5V supply with an approximately 10k resistor. : The logic of input signal is high-active. The DIP-IPM input signal section integrates a 3.3k (min) pull-down resistor. If using external filtering resistor, ensure the voltage drop of ON signal not below the threshold value. : To prevent malfunction of protection, the wiring of A, B, C should be as short as possible. : Please set the filter R1* C4 time constant such that the IGBT can be interrupted within 2s. : Each capacitor should be located as nearby the pins of the DIP-IPM as possible. : To prevent surge destruction, the wiring between the smoothing capacitor and the P-N1 pins should be as short as possible. Approximately a 0.1~0.22F snubber capacitor between the P-N1 pins is recommended. : Make external wiring connection between VNO and VNC terminals as shown in Fig.5. : Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and leave another one open. : To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between each control supply terminals. : The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.43V to max.0.53V). : OR logic output level should be set up the same rating of short circuit trip level (Vsc(ref): min.0.43V to max.0.53V). Jun. 2005

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